Hardware accelerator for hypergraph processing and operating method thereof
US12339775B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Dec 22, 2022 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | May 24, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/1016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention relates to a hardware accelerator for hypergraph processing and its operating method, the hardware accelerator comprising: a data loader: for, in the presence of a data-centric load-trigger-reduce execution model, reading hypergraph partition data from an off-chip memory successively according to hypergraph data structure and an order of hypergraph partitions; an address translator, for deploying the hypergraph data into a private register of a processor and/or into a buffer memory according to a priority level of loaded data, and recording corresponding offset information; a task trigger, for generating computing tasks according to the loaded data, and scheduling the computing tasks into the processor; the processor, for receiving and executing the computing tasks; a reducer, for scheduling intermediate results into a first-priority-data reducer unit or a second-priority-data reducer unit depending on the priority level of the data so as to execute a reducing operation for the intermediate results. In view of the shortcomings of task-centric hardware accelerators, the present invention can prevent any possible data conflict during parallel execution of multip…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.