Circuit device with multiple parallel data paths
US12339795B2 · kind B2 · utility
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Key dates
| Filing date | Feb 20, 2024 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Feb 20, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4027
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) includes first and second memory devices and a bridge. The IC also includes a first interconnect segment coupled between the first memory device and the bridge. The IC further includes a second interconnect segment coupled between the first and second memory devices, and a third interconnect segment coupled between the bridge and the second memory device. The IC includes a first DMA circuit coupled to the first interconnect segment, and a second DMA circuit coupled to the second interconnect segment. A fourth interconnect segment is coupled between the first and second DMA circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.