Multi-rail sense circuit with pre-charge transistors and memory circuit incorporating the sense circuit
US12340841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2023 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Jul 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/1673
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Disclosed are a sense circuit and memory structure incorporating the sense circuit. The sense circuit is connected to voltage rails at VDD1 and VDD2, respectively, where VDD2˜½*VDD1. During a sensing operation, VDD1 provides power to develop a voltage differential between Vdata and Vref on sense nodes. A voltage comparator samples Vdata and Vref and, based on a detectable voltage differential (minVdiff), outputs a data output value. To increase the speed at which minVdiff is reached, an equalization process is performed at the initiation of the sensing operation and includes using pre-charge transistors to quickly equalize the sense nodes to VDD2. Following equalization, Vdata and Vref only need to be pulled up or down from VDD2. Thus, minVdiff is reached faster and sampling by the voltage comparator can be performed earlier in time, reducing the overall time required for performing the sensing operation and for powering the sense circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.