Shift register unit, drive control circuit, display device and driving method
US12340855B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2022 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | May 26, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0286
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A shift register unit includes: an input circuit configured to provide an input signal to a first node in response to a first clock signal; a reset circuit configured to provide a first reference signal to a second node in response to a second clock signal; a first control circuit configured to provide the second clock signal to the second node in response to a first control signal; an output circuit configured to provide a third clock signal to a drive output terminal in response to a signal of the first node, and provide a second reference signal to the drive output terminal in response to a signal of the second node; where a duration of an active level of the first control signal is longer than a duration of an active level of a signal of the drive output terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.