Patent · US Active

Controlling and powering multiple chips

US12341514B1 · kind B1 · utility

0Cited by

5References

30Claims

0Family size

Assignee

Auradine, Inc. · US

Inventors

Shahriar Ilislamoo · San Jose, US
David Carlson · Waukesha, US
Barun Kar · Sunnyvale, US
Darshan Shah · Innsbruck, AT

Key dates

Filing date	Jan 23, 2025
Grant date	Jun 24, 2025
Priority date	—
Expiry date	Jan 23, 2045

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/08
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

An electronic circuit includes: an event detector logic circuit; a computing device; and a plurality of integrated circuit (IC) chips that are electrically connected in parallel between at least one control bus configured to provide input signals and the event detector logic circuit. The event detector logic circuit is configured to: receive a plurality of output signals from the plurality of IC chips, generate a data output signal that includes data obtained from a first output signal of the plurality of output signals, and transmit the data output signal to the computing device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.