Delay-locked loop, delay locking method, clock synchronization circuit, and memory
US12341515B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 16, 2023 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Sep 20, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0816
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Provided are a delay-locked loop (DLL), a delay locking method, a clock synchronization circuit, and a memory. The DLL includes: a frequency division module, configured to receive an input clock signal, perform frequency division on the input clock signal, and output an intermediate clock signal; a first adjustable delay line, configured to receive the intermediate clock signal, adjust and transmit the intermediate clock signal, and output a synchronous clock signal; a delay module, configured to receive the input clock signal, perform delay transmission on the input clock signal, and output a sampling clock signal; and a latching module, configured to receive the sampling clock signal and the synchronous clock signal, latch the synchronous clock signal on the basis of the sampling clock signal, and output a group of target clock signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.