Triple-path clock and data recovery circuit, oscillator circuit and method for clock and data recovery
US12341522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2024 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Feb 1, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L2207/06
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.