D/A converter with resistive interpolation
US12341529B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Aug 25, 2021 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Aug 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/76
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog converter that outputs an analog value representing a digital value includes a decoding stage and an interpolation stage. The decoding stage defines upper and lower bounds and the interpolation stage outputs an interpolated value that is between the upper and lower bounds. The upper and lower bounds are based on a most-significant portion of the digital value. The interpolation stage selects the interpolated value based on the least-significant portion of the digital value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.