Memory array structure
US12342550B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jul 23, 2020 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Mar 22, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B63/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention disclosures a memory array structure, comprising an array composed of multiple memory devices arranged in rows and columns, each of the rows is set with a row leading-out wire, and each of the columns is set with a column leading-out wire, memory devices are correspondingly positioned at intersection points of each row leading-out wire and each column leading-out wire; wherein, the first terminal of each of the memory devices is individually connected to the row leading-out wire of the same row, and the second terminal of each of the memory devices is connected to a first terminal of a switch in the same column, the second terminal of the switch is connected to the column leading-out wire of the same column; wherein, each of the rows is set with one to multiple the switches, and the first terminal of each of the switches is connected to one to all of the second terminals of the memory devices in the same column. The advantage of the present invention is that the corresponding analog currents output of input signals of different specified rows according to multiply-accumulate operation requirements of each of the columns can be obtained simultaneously, thus mul…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.