Array substrate and display panel including electrically connected gates
US12342620B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 2021 |
| Grant date | Jun 24, 2025 |
| Priority date | — |
| Expiry date | Aug 4, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/481
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An array substrate includes a base substrate, a driving circuit layer, and a functional device layer which are sequentially stacked; the driving circuit layer is provided with first driving circuits, and each first driving circuit at least includes a driving transistor; and the driving circuit layer includes a first gate layer, a first gate insulation layer, a semiconductor layer, a second gate insulation layer, a second gate layer, an interlayer dielectric layer, and a source-drain metal layer which are sequentially stacked on one side of the base substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.