Patent · US Active

Memory wear leveling

US12346249B2 · kind B2 · utility

0Cited by
2References
20Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJan 11, 2023
Grant dateJul 1, 2025
Priority date
Expiry dateJan 11, 2043

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F2212/7211
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

In some examples, based on the information relating to the wear of physical memories in computer nodes of the distributed system, a system initiates a migration of a memory page from a first physical memory in a first computer node to a second physical memory in a second computer node. As part of the migration, the system updates a mapping between a first address space accessible by programs in the distributed system and a physical address space comprising memory locations in the physical memories.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.