Semiconductor memory device and methods of operation
US12346573B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2022 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jan 30, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/002
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array, a row hammer management circuit and a control logic circuit. The memory cell array includes a plurality of memory cell rows. The row hammer management circuit counts the number of instances of access of each of the memory cell rows, such as in response to the receipt of an active command, to store the counted values in count cells of each of the memory cell rows as count data and, in response to a first command, initiates an internal read-update-write operation to read the count data, to update the read count data, and to write the updated count data in the count cells. The control logic circuit may performs an internal write operation to write the updated count data in the count cells during a second write time interval that is smaller than a first write time interval associated with a normal write operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.