Testing integrated circuit designs with accelerated replay
US12346643B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Mar 30, 2021 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | May 2, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A technique to stress test an integrated circuit design under test in a simulation environment may include running a simulation that includes providing bus interface transactions and idle cycles on a bus interface of an integrated circuit design. The technique may further include capturing bus interface activity on the bus interface during the simulation to generate a stimulus file and replaying the simulation by executing a test bench driver that reads the stimulus file and injects the bus interface transactions with modified idle cycles onto the bus interface of the integrated circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.