Integrated circuit memory devices having efficient row hammer management and memory systems including the same
US12347477B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 1, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Oct 2, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device includes a memory cell array with a plurality of rows of memory cells therein, and a row hammer management (RHM) circuit including a hammer address queue. The RHM circuit is configured to: (i) receive first access row addresses from an external memory controller during a reference time interval, (ii) store a first row address randomly selected from the first access row addresses and second row addresses consecutively received from the memory controller after selecting the first row address, in the hammer address queue as candidate hammer addresses, and (iii) sequentially output the candidate hammer addresses as a hammer address. A refresh control circuit is provided to receive the hammer address and to perform a hammer refresh operation on one or more victim memory cell rows, which are physically adjacent to a memory cell row corresponding to the hammer address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.