Semiconductor package and substrate for semiconductor package
US12347759B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 2, 2022 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Aug 30, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3512
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a substrate; a semiconductor chip on a first surface of the substrate; and a plurality of external connection terminals on a second surface of the substrate that is opposite to the first surface. The substrate includes a plurality of wirings configured to electrically connect the semiconductor chip and the plurality of external connection terminals. The plurality of wirings includes a first wiring, and the first wiring includes a first portion and a second portion connected to each other, the second portion overlapping an edge of the semiconductor chip in a vertical direction that is perpendicular to the first surface of the substrate. A second width of the second portion is greater than a first width of the first portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.