Method and apparatus for through interposer die level interconnect with thermal management
US12347762B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 2021 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Feb 1, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/49833
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic assembly is disclosed. The electronic assembly includes a first attachment layer, a second attachment layer, a first interposer redistribution layer, a second interposer redistribution layer, at least one of a thermal spreader layer or a thermal management layer, and an interposer cavity. The interposer further includes an interconnect header fixed within the interposer cavity comprising a plurality of interconnect filaments configured to electrically couple to at least one of the first interposer redistribution layer or the second interposer redistribution layer. The interconnect header is generated by applying electrically conductive filaments on a plurality of wafers, thinning the wafers, stacking the wafers, attaching the wafers into a wafer stack, and dicing the wafer stack.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.