Packaging of three-dimensional integrated circuit by encapsulation with copper posts and double sided redistribution layer
US12347763B2 · kind B2 · utility
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1References
15Claims
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Key dates
| Filing date | Dec 14, 2020 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Feb 13, 2042 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01F1/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package. In some embodiments, the package has a top surface and a bottom surface, and includes: a semiconductor die having a front surface, a back surface, and a plurality of edges; a mold compound, on the back surface of the die and the edges of the die; a plurality of first conductive elements extending through the mold compound on the back surface of the die to the top surface of the package; and a plurality of second conductive elements on the bottom surface of the package.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.