Power-failure hold circuit, power supply protection method and apparatus, and power supply control circuit
US12348026B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 11, 2024 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jan 11, 2044 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
A power-fail hold-up circuit includes: a first energy storage circuit, including multiple capacitors connected in parallel, the multiple capacitors being used to store energy and to provide reverse power to the server; a second energy storage circuit, including an inductor and a first switching transistor, wherein the inductor and the first switching transistor are sequentially connected in series between a positive pole of the input bus and a negative pole of the input bus, and the inductor is used to store energy to boost a voltage to a target voltage; and a third energy storage circuit, including a second switching transistor and an energy storage capacitor, wherein the second switching transistor and the energy storage capacitor are sequentially connected in series between the inductor and the negative pole, the inductor is used to charge the energy storage capacitor, and the energy storage capacitor provides reverse power to the server.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.