Programmable logic block with multiple types of programmable arrays and flexible clock selection
US12348224B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Feb 7, 2024 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Feb 7, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/20
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.