Frequency multiplier for phase rotation
US12348233B2 · kind B2 · utility
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11References
20Claims
0Family size
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Key dates
| Filing date | Oct 4, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Oct 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K2005/00019
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A frequency multiplier includes a first digitally controlled delay line (DCDL) configured to receive a first clock signal and generate a second clock signal by changing a phase of the first clock signal, a multiplying delay-locked loop (MDLL) configured to generate a third clock signal by multiplying a frequency of the second clock signal, and a DCDL calibration circuit configured to receive the second clock signal and generate a gain signal for adjusting a gain of the first DCDL where a difference between a maximum delay and a minimum delay of the first DCDL is substantially equal to a period of the third clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.