Sampler circuit for high speed serializer/deserializer
US12348256B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Jan 3, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45212
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an example, a circuit includes a differential input circuit having a first input at a first capacitor terminal and a second input at a second capacitor terminal. The differential input circuit includes a first transistor having a first transistor control terminal and first and second terminals. The differential input circuit includes a second transistor having a second transistor control terminal and first and second terminals, the first terminals of the first and second transistors coupled together. The circuit includes a first capacitor having the first capacitor terminal and having another terminal coupled to the first transistor control terminal. The circuit also includes a second capacitor having the second capacitor terminal and having another terminal coupled to the second transistor control terminal. The circuit includes a first offset correction input coupled to the first transistor control terminal and a second offset correction input coupled to the second transistor control terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.