Joint sample rate offset and symbol timing offset correction
US12348350B2 · kind B2 · utility
0Cited by
5References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Oct 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2671
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver has a sample rate converter that outputs samples of orthogonal frequency division multiplexing symbols. The receiver includes a fast Fourier transform engine that receives the samples and converts them into a plurality of frequency domain sub-carriers. A timing control circuit generates a timing error and controls the sample rate converter to adjust a sample rate of the orthogonal frequency division multiplexing symbols based at least in part on the timing error.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.