Clock frequency deviation detector with closed-loop calibration
US12348606B2 · kind B2 · utility
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29Claims
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Key dates
| Filing date | Mar 15, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Apr 3, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R23/06
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
An apparatus, including: a switched capacitor configured to generate a switched capacitor voltage based on an input clock signal and a current; a current digital-to-analog converter (DAC) configured to generate the current based on a first digital signal; a first reference voltage generator configured to generate a first reference voltage; and a first voltage comparing device configured to generate a first frequency deviation detection signal based on a comparison of the switched capacitor voltage to the first reference voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.