Integrated circuit transceiver array synchronization
US12348607B2 · kind B2 · utility
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12References
22Claims
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Key dates
| Filing date | Jun 30, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Oct 5, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0491
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Transceiver array synchronization by receiving a clock signal and at least one synchronization pulse signal at each transceiver IC of a plurality of transceiver integrated circuit (IC) subarrays, wherein each transceiver IC subarray contains a respective set of serially connected transceiver ICs; and synchronizing the transceiver IC with other transceiver ICs of the respective set of serially connected transceiver ICs by resetting a delta-sigma modulator (DSM) circuit to a predetermined state in accordance with the received at least one synchronization pulse signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.