Transistor and its method of manufacture
US12349405B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Nov 21, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6736
Abstract
A transistor is disclosed, comprising: a layer of semiconductor material comprising a first portion, a second portion, and a third portion connecting the first portion to the second portion and providing a semiconductive channel between the first portion and the second portion; a conductive first terminal covering and in electrical contact with said first portion of the layer of semiconductor material; a conductive second terminal covering and in electrical contact with said second portion of the layer of semiconductor material; a conductive gate terminal comprising a first overlapping portion covering at least part of the first terminal, and a channel portion covering the third portion of the layer of semiconductor material; and a layer of a first dielectric material, having a first dielectric constant, arranged between the first overlapping portion and the first terminal, and between the channel portion of the gate terminal and the third portion of the layer of semiconductor material. The transistor further comprises a layer of a second dielectric material having a second dielectric constant, the second dielectric constant being lower than the first dielectric constant, the layer…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.