Array substrate and liquid crystal display panel
US12349462B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2023 |
| Grant date | Jul 1, 2025 |
| Priority date | — |
| Expiry date | Oct 31, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG02F2201/501
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An embodiment of the present application discloses an array substrate and a liquid crystal display panel. The array substrate uses a first barrier layer including a first aperture in an aperture region. The first barrier layer is at least correspondingly disposed in a thin film transistor disposing region and a gate driver on array circuit region. The first barrier layer is configured to block the alkaline cation from spreading along a direction to the active layer. Along a direction at a right angle from the substrate to the active layer, a depth by which the alkaline cation enters the first barrier layer is less than or equal to 20 Å.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.