Capacitance measurement circuit
US12352794B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jul 26, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R27/2605
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A capacitance measurement circuit includes an analog front-end (AFE) circuit with current mirror circuits, a parasitic capacitor, an AD converter, an output shift register, and a controller. The controller disconnects a capacitor to be measured and connects one current mirror circuit to record an AFE output voltage VN collected at an inverting input terminal of the AD converter, then connects the capacitor to be measured to collect an AFE output voltage VP at a non-inverting input terminal of the AD converter, and converts a value of (VP−VN) into a first digital signal; determines, based on the value of the first digital signal, a connection number m of the current mirror circuits, controls the analog front-end circuit to connect m current mirror circuits, and repeat the steps to obtain a second digital signal; and shift the second digital signal based on the connection number m to obtain a capacitance measurement value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.