Current measurement architecture
US12352826B2 · kind B2 · utility
0Cited by
4References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | May 4, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Various implementations described herein are related to a device with fabrication test circuitry having transistors arranged in a parallel branch configuration between a supply voltage and a single pad. In some applications, each transistor in an off-current branch may be separately deactivated so as to test leakage current applied to the pad by way of the off-current branch, and also, each transistor in an on-current branch may be deactivated so as to further test the leakage current applied to the pad by way of the off-current branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.