Memory device PPR failure handling system
US12353282B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jan 31, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1441
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device Post Package Repair (PPR) failure handling system includes a memory device having a first memory subsystem, and a memory management subsystem coupled to the memory device. The memory management subsystem identifies a first PPR request to perform first PPR operations on the first memory subsystem, and performs first PPR operations on the first memory subsystem based on the first current PPR request. The memory management subsystem may determine that the first PPR operations on the first memory subsystem have failed and, in response, increment a first PPR failure counter for the first memory subsystem, If, following the incrementing the first PPR failure counter for the first memory subsystem, the memory management subsystem determines that the first PPR failure counter for the first memory subsystem has reached a PPR failure count threshold, the memory management subsystem disables use of the memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.