Quantum circuit construction with simultaneously entangling gates in trapped-ion quantum computers
US12353957B2 · kind B2 · utility
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Key dates
| Filing date | Jul 11, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Dec 7, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N10/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of performing computation using an ion trap quantum computing system including a classical computer, a system controller, and a quantum processor includes computing, by the classical computer, a circuit that implements a selected set of gate operations, using one or more efficient arbitrary simultaneous entangling (EASE) gates, implementing, by the system controller, the computed circuit on the quantum processor, measuring, by the system controller, population of qubit states in the quantum processor, and outputting, by the classical computer, the measured population of qubit states in the quantum processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.