Sparse rendering in computer graphics
US12354185B2 · kind B2 · utility
0Cited by
3References
12Claims
0Family size
Assignee
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Key dates
| Filing date | Jan 29, 2024 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jan 29, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T17/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A graphics processing system includes a tiling unit configured to tile a scene into a plurality of tiles. A processing unit identifies tiles of the plurality of tiles that are each associated with at least a predetermined number of primitives. A memory management unit allocates a portion of memory to each of the identified tiles and does not allocate a portion of memory for each of the plurality of tiles that are not identified by the processing unit. A rendering unit renders each of the identified tiles and does not render tiles that are not identified by the processing unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.