Pixel and display device including the same
US12354536B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2024 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jun 14, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/021
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A pixel may include first to third sub-pixels including a first transistor connected to a first power node, a second node, and a first node, a second transistor connected to a data line, the first node, and a first scan line, a third transistor connected to a reference voltage node, the first node, and a second scan line, a fourth transistor connected to a third node, a first initialization voltage node, and a third scan line, a fifth transistor connected to the first power node, the first transistor, and a first emission control line, a sixth transistor connected to the second node, the third node, and a second emission control line, and a first capacitor between the first node and the second node. Any one among reference voltage nodes connected to the first to third sub-pixels may be electrically separated from the other reference voltage nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.