Memory devices and methods thereof for managing row hammer events therein
US12354637B2 · kind B2 · utility
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20Claims
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Key dates
| Filing date | Jun 26, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Sep 27, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array having a plurality of rows of memory cells therein, and a row hammer managing circuit, which is configured to detect a row hammer address based on a pre row hammer address, and each of a plurality of input row addresses associated with a plurality of accesses during a monitoring period for monitoring the plurality of accesses to a plurality of the rows of memory cells. A refresh control circuit is provided and is configured to perform a refresh operation on a memory cell row physically adjacent to a memory cell row corresponding to the row hammer address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.