Memory device refresh operations
US12354640B2 · kind B2 · utility
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4References
20Claims
0Family size
Assignee
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Key dates
| Filing date | Feb 17, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Feb 2, 2044 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a memory device, a control circuit detects determines an aggressor row address, indicating an aggressor row of a memory cell array, at a random time. The aggressor row address or a value derived from the aggressor row address is stored in a queue. The control circuit controls a refresh operation of one or more victim rows based on the aggressor row address in response to a targeted refresh command.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.