Semiconductor storage device
US12354677B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 20, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Dec 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/0483
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a semiconductor storage device includes memory cell transistors, and a word line electrically connected to the memory cell transistors. The device further includes a voltage generator configured to generate a first voltage transferred to the word line, the voltage generator including a voltage divider configured to divide the first voltage with first and second resistance elements, the first or second resistance element being a variable resistance element that receives a first digital signal indicating a resistance value and is changeable to the resistance value. The device further includes a control unit configured to output the first digital signal, wherein the control unit outputs the first digital signal such that a theoretical waveform of the first voltage in boosting the first voltage in an erasing verifying operation is different from a theoretical waveform of the first voltage in boosting the first voltage in a reading operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.