Error correction code circuit, memory device including error correction code circuit, and operation method of error correction code
US12354689B2 · kind B2 · utility
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6References
20Claims
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Key dates
| Filing date | Oct 6, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Oct 6, 2043 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell array and an error correction code (ECC) circuit. The ECC circuit, which is configured to correct an error in a data code read out from the memory cell array, includes: (i) a syndrome calculating unit configured to operate a plurality of syndromes based on the data code and an H-matrix, (ii) an error location detecting unit configured to generate an error vector based on the plurality of syndromes, and (iii) an error correcting unit configured to correct an error within the data code based on the error vector, and output corrected data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.