Under chip bridge
US12354964B1 · kind B1 · utility
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Key dates
| Filing date | Aug 2, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Dec 1, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06513
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, semiconductor products and methods for semiconductor packages, specifically under chip bridge system-in-packages, are provided that allow one or more bridges to connect two or more dies. For example, high density connections of two or more dies may be connected with an under chip bridge, all of which may be placed on a substrate to form a system-in-package semiconductor package. Various embodiments include methods of manufacturing such packages that include utilizing a flat semiconductor along with bumping operations that may use single sizes of bumping.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.