Integrated circuit control apparatus and method
US12355434B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Jan 9, 2024 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Feb 29, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/56
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus includes an enable circuit having a first input configured to receive a serial data in (SDI) signal, a second input configured to receive a not chip select (nCS) signal, a third input configured to receive a hold (HLD) signal, and an output configured to generate an internal enable signal for controlling a power-up process and a power-down process of an integrated circuit, and a digital core circuit configured to generate the HLD signal after the integrated circuit is powered up by the SDI signal and the nCS signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.