Phase interpolator circuit, reception circuit, and semiconductor integrated circuit
US12355449B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 13, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Sep 6, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/081
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.