Interleaved analog-to-digital converter (ADC) gain calibration
US12355458B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 15, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Jun 15, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/0678
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit may include a full-scale reference generation circuit that corrects for variation in the gain or full scale of a set of interleaved analog-to-digital converters (ADCs). Notably, the full-scale reference generation circuit may provide a given full-scale or reference setting for a given interleaved ADC, where the given full-scale setting corresponds to a predefined or fixed component and a variable component (which may specify a given full-scale correction for a given full scale). For example, the full-scale reference generation circuit may include a full-scale reference generator replica circuit that outputs a fixed current corresponding to the fixed component. Furthermore, the full-scale reference generation circuit may include a full-scale reference generator circuit that outputs a first voltage corresponding to the given full-scale setting based at least in part on the fixed current and a variable current that, at least in part, specifies the given full-scale correction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.