System and method for calibrating weighting errors in split capacitance successive approximation analog-to-digital converters
US12355461B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 22, 2023 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Apr 3, 2044 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/804
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to the field of microelectronics and solid-state electronics, and in particular to a calibration system and method for weighting errors brought about by parasitic capacitance in split capacitor-based successive approximation analog-to-digital converters. The method uses an MSB array that does not add additional capacitors, only a switch SM to reduce the comparator design difficulty. Meanwhile, an LSB array may add a calibration DAC array CA including a binary array of P-bit unit capacitors, a calibration structure Cfraq, and a ground switch Sk. The calibration structure Cfraq includes four unit capacitors and two switches S1 and S2. By controlling the switches S1 and S2 different capacitance values can be generated to reduce the chip area consumption. This structure can reduce the error to LSB/4 and the weighting error of the ADC, and increases the effective number of bits of the ADC without excessively increasing comparator gain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.