Patent · US Active

Memory and method for preparing memory

US12356602B2 · kind B2 · utility

0Cited by
5References
14Claims
0Family size

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Inventors

Key dates

Filing dateFeb 10, 2022
Grant dateJul 8, 2025
Priority date
Expiry dateSep 5, 2043

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D84/85

Abstract

A memory and a method for preparing a memory are provided. The method for preparing the memory includes: providing a substrate, in which the substrate includes a first N-type active region and a first P-type active region; forming an epitaxial layer covering the first P-type active region, in which the epitaxial layer exposes the first N-type active region; simultaneously forming a first gate dielectric layer covering the first N-type active region and a second gate dielectric layer covering the epitaxial layer, in which a thickness of the first gate dielectric layer is substantially the same as a thickness of the second gate dielectric layer; forming a first gate covering the first gate dielectric layer to form a first N-channel Metal Oxide Semiconductor (NMOS) device; and forming a second gate covering the second gate dielectric layer to form a first P-channel Metal Oxide Semiconductor (PMOS) device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.