Memory device and manufacturing method therefor
US12356605B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 8, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Dec 23, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6735
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A memory device and a manufacturing method therefor. A film-stack structure is formed on a substrate, the film-stack structure includes sacrificial layers and active layers alternately stacked in a first direction. Part of the film-stack structure located in a first area is removed. A plurality of first grooves spaced apart from each other and extend in a second direction are formed, where the substrate is exposed from the first grooves to divide the active layers located in the first area into a plurality of active pillars spaced apart from each other. The sacrificial layers located in the first and second areas are removed. Part of the active layers located in the second area is removed, to form a plurality of step-shaped connection layers on an end of the second area away from the first area. Gate material layers are formed to cover the connection layers and the active pillars.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.