Semiconductor device including vertical channel pattern surrounded by protection pattern
US12356615B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 14, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Dec 10, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/50
Abstract
A semiconductor device includes a memory cell region positioned on a substrate and comprising a real memory cell region and a dummy memory cell region; and a connection region extending in a first direction parallel to a surface of the substrate in the memory cell region. The dummy memory cell region includes a plurality of dummy vertical channel structures spaced apart from each other. Each of the plurality of dummy vertical channel structures includes a vertical channel pattern in contact with the substrate while penetrating a stack structure comprising a plurality of insulating layers and a plurality of gate electrodes repeatedly stacked in a third direction perpendicular to a surface of the substrate. A protection pattern is disposed to surround the vertical channel pattern of at least one of the plurality of dummy vertical channel structures.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.