Fin height and STI depth for performance improvement in semiconductor devices having high-mobility p-channel transistors
US12356710B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 26, 2021 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Feb 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76229
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method includes providing a substrate having a first semiconductor material; creating a mask that covers an nFET region of the substrate; etching a pFET region of the substrate to form a trench; epitaxially growing a second semiconductor material in the trench, wherein the second semiconductor material is different from the first semiconductor material; and patterning the nFET region and the pFET region to produce a first fin in the nFET region and a second fin in the pFET region, wherein the first fin includes the first semiconductor material and the second fin includes a top portion over a bottom portion, wherein the top portion includes the second semiconductor material, and the bottom portion includes the first semiconductor material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.