Array substrate and manufacturing method thereof, and display panel
US12356717B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | Apr 24, 2042 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/451
Abstract
The present disclosure provides an array substrate and a manufacturing method thereof, and a display panel. The array substrate includes an oxide semiconductor layer, a gate insulating layer, a gate electrode, an interlayer insulating layer, and a source-drain electrode metal layer located on a substrate. Wherein the oxide semiconductor layer includes a channel region and conductive regions, the gate insulating layer is respectively overlapped with the conductive regions on both sides of the channel region, and an orthographic projection of a part of the gate electrode corresponding to the oxide semiconductor layer on the substrate falls within a range of an orthographic projection of the channel region on the substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.