Array substrate and display panel having fanout lines having different resistances
US12356721B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Dec 30, 2022 |
| Grant date | Jul 8, 2025 |
| Priority date | — |
| Expiry date | May 22, 2043 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/131
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
The present application provides an array substrate and a display panel. A connecting area is located between a display area and a fanout area. A plurality of connecting lines and a plurality of coupling lines are located in the connecting area. Overlapping areas between the plurality of connecting lines and the plurality of coupling lines are negatively correlated with resistances of a plurality of fanout lines electrically connected to the plurality of connecting lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.