Patent · US Active

Split floating diffusion pixel layout design

US12356741B2 · kind B2 · utility

0Cited by
1References
41Claims
0Family size

Assignee

Inventor

Key dates

Filing dateOct 31, 2022
Grant dateJul 8, 2025
Priority date
Expiry dateNov 18, 2043

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10F39/813

Abstract

A pixel array includes pixel circuits including a first pixel circuit having a first split floating diffusion receiving charge from first and third photodiodes through first and third transfer transistors, and a second split floating diffusion receiving the charge from second and fourth photodiodes through second and fourth transfer transistors. A first shared gate structure includes gates of first transfer transistors of first and second pixel circuits. A third shared gate structure includes gates of third transfer transistors of the first and second pixel circuits. A second shared gate structure includes gates of second transfer transistors of first and third pixel circuit. A fourth shared gate structure includes gates of fourth transfer transistors the first and third pixel circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.