Hardware accelerator for execution of instruction set of recurrent neural network, data processing method, system-level chip, and medium thereof
US12360766B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 24, 2023 |
| Grant date | Jul 15, 2025 |
| Priority date | — |
| Expiry date | Jul 17, 2043 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerator for running an instruction set of a recurrent neural network, a data processing method, a system-level chip, and a medium are provided. The hardware accelerator is configured to process the instruction set. The instruction set includes: a data flow control instruction used for performing data flow control; a general-type computing instruction used for performing general-type computation to implement general-type computation in the recurrent neural network; a special-type computing instruction used for performing special-type computation to implement special-type computation in the recurrent neural network; an exponential shift instruction used for performing exponential shifting to implement data normalization during computation of the recurrent neural network; and a data transfer instruction used for performing data transfer to implement data transfer operations between different registers as well as data transfer operations between registers and memories during computation of the recurrent neural network.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.