Adaptive internal error scrubbing and error handling

US12360847B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Kuljit S. Bains · DuPont, US
• Kjersten E. Criss · Portland, US
• Rajat Agarwal · Portland, US
• Omar Avelar Suarez · Zapopan, MX
• Subhankar Panda · Portland, US
• Theodros Yigzaw · Sherwood, US
• Rebecca Z. Loop · Hillsboro, US
• John G. Holm · Beaverton, US
• Gaurav Porwal · Kanchinakote, IN

Key dates

• Filing date: Sep 26, 2020
• Grant date: Jul 15, 2025
• Expiry date: Oct 17, 2040

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C2029/0411
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory subsystem with error checking and scrubbing (ECS) logic on-device on the memory can adapt the rate of ECS operations in response to detection of errors in the memory when the memory device is in automatic ECS mode. The ECS logic can include an indication of rows of memory that have been offlined by the host. The ECS logic can skip the offlined rows in ECS operation counts. The ECS logic can include requests or hints by the host to have ECS operations performed. An internal address generator of the ECS logic can select between generated addresses and the hints. The system can allow a memory controller to detect multibit errors (MBEs) related to a specific address of the associated memory. When the detected MBEs indicate a pattern of errors, the memory controller triggers a row hammer response for the specific address.